1. Field of the Invention
The present invention relates to analysis of a semiconductor integrated circuit, and particularly to a technique for extracting parasitic capacitances and resistances.
2. Description of Related Art
In the technical fields for extracting parasitic capacitances and resistances, delay calculation, and SI (crosstalk) analysis, the effect of noise on a power supply interconnection is known. However, the effect of power supply noise on a signal delay problem was negligible in terms of precision since power supply voltage is high and parasitic capacitances between power supply interconnections and resistances are small.
However, the effect of a voltage drop due to power supply noise on delay calculation and timing design increases greater so that it has not become negligible in association with increase in the parasitic capacitances and resistances due to increase in an operation frequency and miniaturization in a manufacturing process, and adoption of a lower power supply voltage. In the delay calculation, it is required to consider a delay variation due to the effect of noise on a power supply line as well as on signal interconnection, although the effect of the power supply noise has been neglected in terms of precision. Therefore, it is necessary to extract a parasitic capacitance and resistance of the power supply interconnection.
Patent Literature 1 discloses a conventional method of extracting parasitic elements. FIG. 1 is a flow chart for a conventional method of extracting parasitic capacitances and resistances in order to simulate performance of an integrated circuit for delay analysis.
In a step 201, interconnections in an integrated circuit are extracted, namely, a net is extracted. A parasitic capacitance of each of interconnections is measured by using a software tool such as “Vampire” commercially available from Candace Design Systems, Inc. (in California). The interconnections represent wiring lines or a net between electronic elements such as transistors in an integrated circuit.
In a step 202, an estimation value of a maximum resistance of each interconnection in the integrated circuit is calculated. That is, the estimation value of the maximum resistance of each interconnection in the integrated circuit is calculated by using the following equation (1):Rest=(intCap×metalRes)/(minMetalCap×minWireWidth)  (1)where Rest is the estimated maximum resistance of the interconnection, intCap is the extracted parasitic capacitance value, metalRes is an estimated resistivity of the interconnection, minMetalCap is an estimated minimum parasitic capacitance value of the interconnection, and minWireWidth is an estimated shortest length of the interconnection. The estimated resistivity, the minimum parasitic capacitance value, and the shortest length of each interconnection can be obtained from a resistivity, a parasitic capacitance, and a length of the interconnection which are dependent on a manufacturing process.
In a step S203, an estimated delay is calculated by using the following equation (2) for each interconnection in the integrated circuit:Delayest=0.5×Rest×intCap+Rest×Cgate  (2)where Delayest is an estimated delay of a signal from one point to another point in the interconnection, and Cgate is an estimated total parasitic capacitance of gates of transistors connected to the interconnection. The estimated total parasitic capacitance is obtained from the manufacturing process.
In another example, the estimated delay in the interconnection can be determined by calculating an estimated parasitic capacitance and an estimated resistance of the interconnection mentioned below.
The parasitic capacitance of the interconnection can be estimated by using the following equation (3):Capest=(maxDist×maxMetalCap)  (3)where Capest is the estimated parasitic capacitance of the interconnection, maxDist is an estimated value of a maximum distance between the interconnections, and maxMetalCap is an estimated maximum parasitic capacitance of the interconnection. The estimated maximum distance can be acquired from a layout, and the maximum parasitic capacitance of the interconnection can be acquired from the manufacturing process.
The resistance of the interconnection can be estimated by using the following equation (4):Rest=(maxDist×metalRes)/minWireWidth  (4)where Rest is the estimated resistance of the interconnection, metalRes is an estimated resistivity of the interconnection, and minWireWidth is an estimated shortest length of the interconnection.
With the use of the calculation results of the equations (3) and (4), the estimated delay of the interconnection in the integrated circuit can be calculated by using the following equation (5):Delayest=0.5×Rest×Capest+Rest×Cgate  (5)where Delayest is the estimated delay of the interconnection, and Cgate is the estimated total parasitic capacitance of gates of transistors connected to the interconnection.
In a step 204, important interconnections are selected. In this example, an interconnection in which the estimated delay of a signal calculated in the step 203 exceeds a threshold value selected in advance is selected and identified as the important interconnection.
In a step 205, a transistor driving the important interconnection, and a transistor receiving a signal propagated on the important interconnection are identified.
In a step 206, a net list including a list of transistors in the integrated circuit is simplified into a small net list by selecting the transistors identified in the step 205.
In a step 207, layout layers connected to the important interconnections are extracted from the entire layout of the integrated circuit. That is to say, all the layers which are electrically connected to the important interconnections are extracted. For example, via-contacts connected to the important interconnections are extracted. In another example, metal contacts relevant to the important interconnections are extracted. The layout layers connected to the important interconnections are extracted by using various software tools available as products such as Vampire. The coordinates of them indicate locations of transistors in the entire layout of the integrated circuit. The coordinates can be used to relate the respective parasitic capacitances and resistances in the layout layers extracted as mentioned below, to specific transistors in the simplified net list.
In a step 208, the respective parasitic capacitances and resistances of the extracted layout layers are extracted. That is to say, measurement is possible by using various software tools commercially available such as Vampire.
In a step 209, the respective extracted parasitic capacitances and resistances of the layout layers are related to the specific transistors in the simplified net list. As mentioned above, the coordinates of a transistor connected to the layout layer extracted in the step 207 can be acquired. By using such coordinates, the respective extracted parasitic capacitances and resistances of the extracted layout layers can be related to the transistors connected to the extracted layout layers in the simplified net list. In a step 210, analysis can be performed.